Selected Qbus Notes and Examples -------- ---- ----- --- -------- Ross Harvey ross@netbsd.org Rev 2, Sun Feb 8 17:20:52 PST 1998 Example design and pinout provided courtesy of Avalon Computer Systems, Inc. Santa Barbara, California. This information is for the proposed NetBSD/VAX IDE/SCSI Q-bus hardware project. This is reference information on q-bus device design. In this directory are: 1. This file 2. Two pages from Avalon's drawings for the A11 (AlphaCard) project. (This was an early 21064 Alpha on a Q-bus board sold to VAX/VMS sites.) -rw-r--r-- 1 ross ross 13465 Feb 8 01:46 QBUS.MADE.EASY -rw-r--r-- 1 ross ross 72741 Feb 8 01:30 fab.a11.ledger.pcl -rw-r--r-- 1 ross ross 72740 Feb 8 01:30 fab.a11.legal.pcl -rw-r--r-- 1 ross ross 72735 Feb 8 01:30 fab.a11.letter.pcl -rw-r--r-- 1 ross ross 35082 Feb 8 15:04 fab.a11.ps.gz -rw-r--r-- 1 ross ross 189431 Feb 8 01:30 qbus.a11.ledger.pcl -rw-r--r-- 1 ross ross 189430 Feb 8 01:30 qbus.a11.legal.pcl -rw-r--r-- 1 ross ross 189425 Feb 8 01:30 qbus.a11.letter.pcl -rw-r--r-- 1 ross ross 88695 Feb 8 02:25 qbus.a11.ps.gz fab.a11 This is the fab drawing for the Avalon a11 qbus board. It gives the qbus mechanical dimensions and instructions to the fab shop. qbus.a11 This is the schematic drawing for the q-bus section of the AlphaCard. The PCL files are really HPGL files with the PCL command to switch into HPGL mode prepended at the beginning. These files use the compressed binary vectors, but they should print just fine on almost any HP laserjet. The PS files can be configured for different page sizes by changing some true/false constants in the first few lines. Basic Qbus Operation ----- ---- --------- The Q bus is a multiplexed address and data bus with an unusual (1.5) volt signal threshold. To build a device that generates interrupts and responds as a slave to I/O page transfers is fairly easy. Signals: Almost all signals are active low, but because the transceivers invert, signals will have a generally positive polarity within the interface circuitry. However, to be consistent with the DEC documentation I will describe the signals as they are present on the Q-bus. ("Asserted" == low) BDAL 21:0 address and data. Called B[] sometimes below. BBS7 L this is a nice one, if the device is in the I/O page, the master asserts this signal, so that slaves don't have to actually compare the 9 high I/O page address bits. The Unibus didn't have this one, although it didn't have as many addresses to decode, either. BWTBT L Write/byte control, except that during the address phase, this signal is asserted to mean that a write will follow. The main distinction between read and write is the assertion of the B DOUT L or B DIN L strobe, so this signal can be ignored during the address phase. BDIN L Read Strobe BDOUT L Write Strobe BRPLY L Slave Handshake signal. BIRQx L x = 4,5,6,7: interrupt requests BIAKI L Interrupt acknowledge in BIAKO L Interrupt acknowledge out (daisy-chained) BDMGI Daisy-chained DMA grant signals. BDMGO BDMR DMA request signal. BINIT Peripheral device reset signal BIRQ4,5,6,7 Interrupt request signals BPOK Power OK signal BREF Not really a refresh signal: this is used in block mode DMA. "Beyond the scope of this document." BSACK Select acknowledge. Used by masters to acknowledge the DMA grant. BWTBT In address phase, indicates an upcoming write, in the data phase, means write just one of the bytes. DMGF, IAKF These are just Avalon's name for the DMGI/O and IAKI/O pairs on the unused P2 connector. They are forwarded so the card can be used in, e.g., a MVII that has Qbus on both halves of a quad board. PIO boards need to forward DMGI/O on both halves, of course. I/O page transfer. The master outputs the address, BBS7 L, and possibly BWTBT L. After a setup time, it asserts BSYNC L. The device will see the BDAL and the control signals set up at least 75 nS prior to BSYNC L. Hold time is 25 nS. In general, you have a CSR switch register that pulls down 8 or 10 resistively pulled-up signals that feed a comparator. The other side of the comparator (for the 8 bit case) gets BDAL 12:5. This consumes 32 bytes of I/O page space, obviously. You can ignore BDAL 21:13. A 10 bit comparator would give you an 8 byte I/O range. On the BSYNC edge you clock the result of the comparator, and you also must save at least some of BDAL 4:0 if you implement more than one register. The CPU will next assert B DIN L. When the slave has the read data (at least almost) ready, the selected slave responds with B RPLY L. Within 125 nS of the assert of B RPLY L, the slave must output the data and hold it until the CPU negates DIN. The slave then negates RPLY and, 0-100 nS later, stops driving BDAL. For writes, the CPU asserts B DOUT L. The slave will have write data set up at least 25 nS prior to receiving the strobe. The data will be held until the slave asserts B RPLY, then the CPU negates DOUT, and the slave then negates RPLY. Interrupts. To request an interrupt, at a particular level, the card asserts interrupt requests as follows: Level Asserted Signals 4 BIRQ4 5 BIRQ4 BIRQ5 6 BIRQ4 BIRQ6 7 BIRQ4 BIRQ6 BIRQ7 The IDE controller should probably just use BIRQ4. First, the slave asserts B IRQx. The CPU responds eventually with BDIN L. After (at least) 125 nS, the device will see B IAKI. At this point, the device has to decide to forward the IAK to device further down the bus, or to eat the IAK and generate its own interrupt. Obviously, this can happen whether or not we actually asserted an IRQ. The device is supposed to monitor the higher levels, and _even if asserting IRQ_, it should still forward the IAK if a higher level device is requesting the bus. The decision should be made with the leading edge of BDIN, to allow any metastable states to settle out prior to the arrival of IAKI. Level Levels Checked 4 BIRQ5 BIRQ6 5 BIRQ6 6 BIRQ7 7 If forwarding the IAKI, the device simply asserts IAKO until IAKI is deasserted. If taking the IAKI, the device asserts B RPLY and drives the vector (0-125 nS after RPLY, better to do 0!) on BDAL. You can program the vector via a HW switch register, or, you can have the device driver set it up via a CSR write. Note that a quad board should wire IAKI to IAKO on the P2 or B tab, in case it is used in a system where the Q bus appears on both A/B (P1/P2) and C/D (P3/P4). You can only count on P3/P4, though. A non-dma board should wire the dma grant through on both P2 and P4. The DMA grant is daisy chained just like IAKI/IAKO. SLOT TO SLOT SPACINGS AND COMPONENT CLEARANCE : Older Q bus, Unibus MV II and MVIII that were upgraded from MVII systems with no box change. 0.50 board to board pitch 0.373 non-conductive component clearance 0.323 conductive component clearance 0.873 two-slot non-conductive clearance 0.823 two-slot conductive clearance BA213 Most MVIII (MV IV?) 0.95 board to board pitch 0.823 non-conductive component clearance 0.773 conductive component clearance SOME Q BUS TIMING SPECS AT SLAVE: control (BS7 WTBT) setup to SYNC 75 hold from SYNC 25 assert reply (s) to negate din (m) 200 min assert reply (s) to assert data (s) 0 min 125 max negate reply (s) to release data (s) 0 min 100 max sync low between cycles 150 min negate reply (s) to sync (m) [next cycle] 300 min WTBT, Data setup to DOUT 25 min RPLY to DOUT (negate) 150 min FROM SLAVE: DIN to DATA 125 max FROM MASTER: [ note, these aren't directly relevent to a slave board ] !SYNC (last cycle) to SYNC 200 min !RPLY (last cycle) to SYNC 300 min SYNC to DIN 100 min Control,ADDR setup to SYNC 150 min Control,ADDR hold after SYNC 100 min RPLY to DATA clock 200 min RPLY to !DIN 200 min 2000 max Pinout. Dec uses an alphabetic assignment, but we gave the pins numbers and, sorry, changed some of the names. So, for example, the DEC AU2 pin assignment for BDAL0 is P4-34, B[0] below. | COMPONENT SIDE | | | | ___ ___ ___ | \_______/ \_______/ \_______/ \_______/ DEC TABS B A B A ACS TABS P1 P2 P3 P4 DEC fingers V1 A1 V1 A1 V1 A1 V1 A1 ACS fingers 35 1 35 1 35 1 35 1 (Dec calls the back side fingers A2 - V2, for ACS they are the even numbers) PIN ASSIGNMENT BY SIGNAL P4 34 B[0] P1 27 N/C P3 26 B[10] P1 28 N/C P3 28 B[11] P1 29 N/C P3 30 B[12] P1 3 N/C P3 32 B[13] P1 30 N/C P3 34 B[14] P1 32 N/C P3 36 B[15] P1 33 N/C P4 5 B[16] P1 34 N/C P4 7 B[17] P1 36 N/C P3 5 B[18] P1 4 N/C P3 7 B[19] P1 5 N/C P4 36 B[1] P1 7 N/C P3 9 B[20] P1 8 N/C P3 11 B[21] P1 9 N/C P3 10 B[2] P2 1 N/C P3 12 B[3] P2 10 N/C P3 14 B[4] P2 11 N/C P3 16 B[5] P2 12 N/C P3 18 B[6] P2 13 N/C P3 20 B[7] P2 14 N/C P3 22 B[8] P2 16 N/C P3 24 B[9] P2 17 N/C P4 26 B[BS7] P2 18 N/C P4 14 B[DIN] P2 19 N/C P4 28 B[DMGI] P2 20 N/C P4 30 B[DMGO] P2 23 N/C P4 23 B[DMR] P2 25 N/C P4 10 B[DOUT] P2 26 N/C P4 22 B[IAKI] P2 27 N/C P4 24 B[IAKO] P2 29 N/C P4 32 B[INIT] P2 3 N/C P4 20 B[IRQ4] P2 32 N/C P4 1 B[IRQ5] P2 33 N/C P4 3 B[IRQ6] P2 34 N/C P3 1 B[POK] P2 35 N/C P4 27 B[REF] P2 36 N/C P4 12 B[RPLY] P2 4 N/C P3 23 B[SACK] P2 5 N/C P4 16 B[SYNC] P2 7 N/C P4 18 B[WTBT] P2 8 N/C P1 15 GND P2 9 N/C P1 21 GND P3 13 N/C P1 31 GND P3 17 N/C P1 6 GND P3 19 N/C P2 15 GND P3 25 N/C P2 21 GND P3 27 N/C P2 31 GND P3 29 N/C P2 6 GND P3 3 N/C P3 15 GND P3 33 N/C P3 21 GND P3 4 N/C P3 31 GND P3 8 N/C P3 6 GND P4 11 N/C P4 15 GND P4 13 N/C P4 21 GND P4 17 N/C P4 31 GND P4 19 N/C P4 6 GND P4 25 N/C P1 1 N/C P4 29 N/C P1 10 N/C P4 33 N/C P1 11 N/C P4 35 N/C P1 12 N/C P4 4 N/C P1 13 N/C P4 8 N/C P1 14 N/C P4 9 N/C P1 16 N/C P1 2 VCC P1 17 N/C P1 35 VCC P1 18 N/C P2 2 VCC P1 19 N/C P3 2 VCC P1 20 N/C P3 35 VCC P1 22 N/C P4 2 VCC P1 23 N/C P2 28 bus.DMGF P1 24 N/C P2 30 bus.DMGF P1 25 N/C P2 22 bus.IAKF P1 26 N/C P2 24 bus.IAKF PIN ASSIGNMENT BY PIN P1 1 N/C P3 1 B[POK] P1 2 VCC P3 2 VCC P1 3 N/C P3 3 N/C P1 4 N/C P3 4 N/C P1 5 N/C P3 5 B[18] P1 6 GND P3 6 GND P1 7 N/C P3 7 B[19] P1 8 N/C P3 8 N/C P1 9 N/C P3 9 B[20] P1 10 N/C P3 10 B[2] P1 11 N/C P3 11 B[21] P1 12 N/C P3 12 B[3] P1 13 N/C P3 13 N/C P1 14 N/C P3 14 B[4] P1 15 GND P3 15 GND P1 16 N/C P3 16 B[5] P1 17 N/C P3 17 N/C P1 18 N/C P3 18 B[6] P1 19 N/C P3 19 N/C P1 20 N/C P3 20 B[7] P1 21 GND P3 21 GND P1 22 N/C P3 22 B[8] P1 23 N/C P3 23 B[SACK] P1 24 N/C P3 24 B[9] P1 25 N/C P3 25 N/C P1 26 N/C P3 26 B[10] P1 27 N/C P3 27 N/C P1 28 N/C P3 28 B[11] P1 29 N/C P3 29 N/C P1 30 N/C P3 30 B[12] P1 31 GND P3 31 GND P1 32 N/C P3 32 B[13] P1 33 N/C P3 33 N/C P1 34 N/C P3 34 B[14] P1 35 VCC P3 35 VCC P1 36 N/C P3 36 B[15] P2 1 N/C P4 1 B[IRQ5] P2 2 VCC P4 2 VCC P2 3 N/C P4 3 B[IRQ6] P2 4 N/C P4 4 N/C P2 5 N/C P4 5 B[16] P2 6 GND P4 6 GND P2 7 N/C P4 7 B[17] P2 8 N/C P4 8 N/C P2 9 N/C P4 9 N/C P2 10 N/C P4 10 B[DOUT] P2 11 N/C P4 11 N/C P2 12 N/C P4 12 B[RPLY] P2 13 N/C P4 13 N/C P2 14 N/C P4 14 B[DIN] P2 15 GND P4 15 GND P2 16 N/C P4 16 B[SYNC] P2 17 N/C P4 17 N/C P2 18 N/C P4 18 B[WTBT] P2 19 N/C P4 19 N/C P2 20 N/C P4 20 B[IRQ4] P2 21 GND P4 21 GND P2 22 bus.IAKF P4 22 B[IAKI] P2 23 N/C P4 23 B[DMR] P2 24 bus.IAKF P4 24 B[IAKO] P2 25 N/C P4 25 N/C P2 26 N/C P4 26 B[BS7] P2 27 N/C P4 27 B[REF] P2 28 bus.DMGF P4 28 B[DMGI] P2 29 N/C P4 29 N/C P2 30 bus.DMGF P4 30 B[DMGO] P2 31 GND P4 31 GND P2 32 N/C P4 32 B[INIT] P2 33 N/C P4 33 N/C P2 34 N/C P4 34 B[0] P2 35 N/C P4 35 N/C P2 36 N/C P4 36 B[1]